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Tables of Contents for Vhdl Coding Styles and Methodologies
Chapter/Section Title
Page #
Page Count
VHDL Overview and Concepts
1
28
What is VHDL
1
1
Level of Descriptions
2
1
Methodology and Coding Style Requirements
3
1
VHDL Types
4
1
VHDL Object Classes
5
4
Constant
6
1
Signal and Variable
7
2
File
9
1
VHDL Design Units
9
11
Entity
10
1
Style
10
1
Comment
11
1
Header
12
1
Generics
12
1
Indentation
13
1
Line length
13
1
Statements per line
13
1
Declarations per line
13
1
Alignment of declarations
14
1
Entity Ports
14
2
Architecture
16
1
Process
17
3
Compilation, Elaboration, Simulation
20
9
Compilation Example
23
1
Simulation Example
24
1
Synthesis Example
25
4
Basic Language Elements
29
62
Lexical Elements
29
9
Identifiers
29
2
Port Identifiers
31
1
Identifier Naming Convension
32
4
Accessing Identifiers Defined in Packages
36
1
Capitalization
37
1
Syntax
38
10
Delimiters
39
1
Literals
40
1
Decimal literals
40
1
Based literals
40
1
Character literals
40
1
String literals
41
1
Bit string literals
41
1
Operators and Operator Precedence
42
1
Logical operators
43
1
Relational Operators
43
1
Shift Operators
44
2
The Concatenation ``&'' Operator
46
1
Remainder and Modulus
47
1
Types and Subtypes
48
30
Scalar Type
49
1
Integer Type and Subtypes
49
2
Enumeration Types
51
1
User Defined Enumeration Types
51
3
Predefined Enumeration Types
54
2
Boolean Type
56
1
Physical types
56
2
Distinct Types and Type Conversion
58
2
Real type
60
1
Composite
61
1
Arrays
61
1
One Dimensional Arrays
61
3
Unconstrained Array Types
64
4
Multi-dimensional Array types
68
2
Anonymous Arrays
70
1
Implicit Functions for Array Declarations
70
3
Array Slices and Ranges
73
1
Records
74
2
Access Type
76
2
File
78
3
Attributes
81
5
Aliases
86
5
Control Structures
91
24
Expression Classification
91
1
Control Structures
92
23
The ``if'' Statement
93
3
The Case Statement
96
3
Rules for the Case Statement
99
4
Latch Inference
103
1
Register Inference
104
1
Loop Statement
104
1
The Simple Loop
105
1
The while loop
106
1
The for loop
107
1
for loop Rules
107
8
Drivers
115
14
Resolution Function
115
2
Drivers
117
6
Definition and Initialization
117
3
Creation of Drivers
120
1
Drivers and Resolved Signal Types
121
1
Driving Data from multiple Processes onto a Non-Resolved Signal
121
2
Ports
123
6
VHDL Timing
129
28
Signal Attributes
129
7
The ``Wait'' Statement
136
7
Delta Time
137
2
wait on sensitivity_list
139
1
wait until condition
139
2
wait for time-expression
141
2
Simulation Engine
143
3
Modeling with Delta Time Delays
146
2
Wait for 0 ns Method
146
1
Concurrent Statements Method
147
1
Use of Variables Method
147
1
VITAL Tables
148
1
Inertial/Transport Delay
148
9
Simulation Engine Handling of Inertial Delay
149
1
Simple View
149
1
Updating Projected Waveforms per LRM 8.4.1
149
8
Elements of Entity/Architecture
157
36
VHDL Entity
157
5
VHDL Architecture
162
31
Process Statement
164
4
Concurrent Signal Assignment Statements
168
1
Conditional Signal Assignment
169
1
Selected Signal Assignment
170
1
Component Instantiation Statement
171
3
Port Association Rules
174
1
Connection
174
2
Type Conversion
176
2
Concurrent Procedure Call
178
1
Generate Statement
179
2
Concurrent Assertion Statement
181
2
Block Statement
183
3
Guarded Signal Assignments
186
7
Subprograms
193
34
Subprogram Definition
193
3
Subprogram Rules and Guidelines
196
16
Unconstrained Arrays in Subprograms
196
2
Interface class declaration
198
3
Subprogram Initialization
201
1
Subprogram Implicit Signal Attributes
202
2
Passing Subtypes
204
1
Drivers in Subprograms
205
1
Signal Characteristics in Procedure Calls
206
2
Side Effects
208
1
Separating High Level Tasks From Low Level Protocols
209
3
Positional and Named Notation
212
1
Subprogram Overloading
212
1
Functions
212
4
Resolution Function
216
2
Operator Overloading
218
2
Concurrent Procedure
220
7
Packages
227
34
Package
227
11
Package Declaration
228
1
Package Body
229
2
Deferred Constant
231
1
The ``use'' Clause
232
3
Signals in Packages
235
1
Resolution Function in Packages
236
2
Subprograms in Packages
238
1
Converting Typed Objects to Strings
238
5
Package Textio
243
7
Printing Objects from VHDL
248
2
Design of a Linear Feedback Shift Register (LFSR)
250
6
Random Number Generation
255
1
Compilation Order
256
5
Compilation Rules on Changes
257
1
Automatic Analysis of Dependencies
257
4
User Defined Attributes, Specification, and Configurations
261
20
Attribute Declarations
261
1
User-Defined Attributes
262
2
Specifications
264
5
Attribute Specifications
264
5
Configuration Specification
269
4
Default Binding Indication
269
1
Explicit Binding Indication in Configuration Specifications
270
3
Configuration Declaration
273
8
Binding with configured components
277
1
Configuration of Generate Statements
277
2
Deferring the Binding of an Instance of a Component
279
2
Design for Synthesis
281
28
Constructs for Synthesis
282
2
Register Inference
284
5
Signals Assignments in Clocked Process
284
1
Variable assignments in clocked process
285
3
Asynchronous Reset or Set of Registers
288
1
Synchronous Reset or Set of Registers
289
1
Combinational Logic Inference
289
7
Latch Inference and Avoidance
292
2
Variable
294
2
State Machine
296
2
RTL State Machine Design Styles
298
7
State Machine Styles
298
6
Safe FSM with No Lock up
304
1
Arithmetic Operations
305
4
Functional Models and Testbenches
309
44
Testbench Modeling
310
11
Testbench Overview
310
3
Testbench Design Methodology
313
1
Validation Plan
313
2
List of errors to be detected
315
1
Architecture block diagram
316
1
Testbench design
316
1
Testbench Architectures
316
1
Typical Testbench Architecture
317
3
FM/BFM Modeling Requirements
320
1
Scenario Generation Schemes
321
32
Scenario Generation Model: VHDL Code
325
1
Waveform Generator
325
2
Client/Server
327
8
Scenario Generation Model: Text Command File
335
11
Scenario Generation Model: Binary Command File
346
1
Generation of Binary Files
347
6
UART Project
353
30
UART Architecture
353
8
UART Transmitter
353
1
General UART Concepts
353
1
UART Transmitter design
354
3
UART Receiver
357
4
UART Testbench
361
22
UART Package
365
3
Transmit Protocol
368
2
Receive Protocol Component
370
1
Transmission Line Component
371
1
Monitor or Verifier Component
372
2
Testbench Entity and Architecture
374
6
Configuration
380
3
Vital
383
12
Vital
384
1
Overview
384
1
Vital Features
384
1
Vital Model
385
10
Pin-to-Pin Delay Modeling Style
386
5
Distributed Delay Modeling Style
391
4
Appendix A VHDL'93 and VHDL'87 Syntax Summary
395
10
Appendix B Package Standard
405
2
Appendix C Package Textio
407
2
Appendix D Std_Logic_Textio
409
2
Appendix E Package Std_Logic_1164
411
4
Appendix F Numeric_Std
415
12
Appendix G Std_Logic_Unsigned
427
2
Appendix H Std_Logic_Signed
429
2
Appendix I Std_Logic_Arith
431
4
Appendix J Std_Logic_Misc
435
4
Appendix K VHDL Predefined Attributes
439
4
Index
443