Product Description: It is widely acknowledged that the cost of validation and testing comprises a s- nificant percentage of the overall development costs for electronic systems today, and is expected to escalate sharply in the future. Many studies have shown that up to 70% of the design development time and resources are spent on functional verification...read more

Product Description: This book on Effective Functional Verification will enable the reader to get a jump start on planning and executing a verification plan using the concepts presented. Case studies are given with analysis and there is coverage of planning and closure aspects.

Product Description: This insightful book will help both novice and experienced verification engineers master the Open Verification Methodology through extensive examples. It describes basic verification principles and explains the essentials of transaction-level modeling.

Product Description: I am glad to see this new book on the e language and on verification. I am especially glad to see a description of the e Reuse Methodology (eRM). The main goal of verification is, after all, finding more bugs quicker using given resources, and verification reuse (module-to-system, old-system-to-new-system etc...read more

Product Description: VLSI Specification, Verification and Synthesis Proceedings of a workshop held in Calgary from 12-16 January 1987. The collection of papers in this book represents some of the discussions and presentations at a workshop on hardware verification held in Calgary, January 12-16 1987...read more

Product Description: Verification isjob one in today's modem design process. Statistics tell us that the verification process takes up a majority of the overall work. Chips that come back dead on arrival scream that verification is at fault for not finding the mistakes...read more

Product Description: This volume contains two distinct, but related, approaches to the verification problem, both based on symbolic simulation. It describes new ideas that enable the use of formal methods, specifically symbolic simulation, in validating commercial hardware designs of remarkable complexity...read more

On Third World streets or First World televisions, Latin America's children are seen but seldom listened to. Child labourers, street children and shanty town kids are portrayed in the West as helpless victims, passive, big-eyed and hungry, besieged by poverty and violence. However, this text argues that if you talk to the children themselves a different picture emerges - one of children as active, energetic and resourceful fighters, struggling to improve their lives, get an education, and earn a living. The book explores the lives of children through their own eyes and voices. It argues that child participation is both a right and a necessity if child-centred social programmes are to succeed. More broadly, harnessing the energy of children could help the region tackle pressing environmental and social problems. Duncan Green talks to children across the continent, watching them at work and play, on the streets or in the home. He interviews children in Brazil, Jamaica, Peru, Columbia, Honduras and Nicaragua, as well as teachers, welfare workers and other adults involved in their lives. He provides comprehensive background research to support his findings, while photographs illustrate the text.

Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. From the Foreword: `With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.' Kurt Keutzer, University of California, Berkeley

Product Description: Model based testing is the most powerful technique for testing hardware and software systems. This book describes the use of models at all the levels of hardware testing. It includes a description of fault models for nanoscaled CMOS technology.

Product Description: This book focuses on Object Orientation Programming and its applications for C++ and SystemVerilog. It includes discussion on why and when certain features should be used. The book also includes an open source verification framework as well as examples.

Product Description: In Test Pattern Generation using Boolean Proof Engines, we give an introduction to ATPG. The basic concept and classical ATPG algorithms are reviewed. Then, the formulation as a SAT problem is considered. As the underlying engine, modern SAT solvers and their use on circuit related problems are comprehensively discussed...read more

Product Description: Improve design efficiency and reduce costs with this practical guide to formal and simulation-based functional verification. Giving you a theoretical and practical understanding of the key issues involved, expert authors including Wayne Wolf and Dan Gajski explain both formal techniques (model checking, equivalence checking) and simulation-based techniques (coverage metrics, test generation)...read more

SystemVerilog for Verification teaches the reader how to use the power of the new SystemVerilog testbench constructs plus methodology without requiring in-depth knowledge of Object Oriented Programming or Constrained Random Testing. The book covers the SystemVerilog verification constructs such as classes, program blocks, C interface, randomization, and functional coverage. SystemVerilog for Verification also reviews some design topics such as interfaces and array types. There are extensive code examples and detailed explanations. The book will be based on Synopsys courses, seminars, and tutorials that the author developed for SystemVerilog, Vera, RVM, and OOP. Concepts will be built up chapter-by-chapter, and detailed testbench using these topics will be presented in the final chapter. SystemVerilog for Verification concentrates on the best practices for verifying your design using the power of the language.  

Product Description: This book presents formal testplanning guidelines with examples focused on creating assertion-based verification IP. It demonstrates a systematic process for formal specification and formal testplanning, and also demonstrates effective use of assertions languages beyond the traditional language construct discussions Note that there many books published on assertion languages (such as SystemVerilog assertions and PSL)...read more

Product Description: This book addresses a means of quantitatively assessing functional verification progress. Without this process, design and verification engineers, and their management, are left guessing whether or not they have completed verifying the device they are designing...read more

Product Description: This book provides an engineering insight into how to provide a scalable and robust verification solution with ever increasing design complexity and sizes. It describes SAT-based model checking approaches and gives engineering details on what makes model checking practical...read more

Product Description: Integrating formal property verification (FPV) into an existing design process raises several interesting questions. This book develops the answers to these questions and fits them into a roadmap for formal property verification – a roadmap that shows how to glue FPV technology into the traditional validation flow...read more

Product Description: Describes a small verification library with a concentration on user adaptability such as re-useable components, portable Intellectual Property, and co-verification.Takes a realistic view of reusability and distills lessons learned down to a tool box of techniques and guidelines.

Product Description: Using the book and the software provided with it, the reader can build his/her own tester arrangement to investigate key aspects of analog-, digital- and mixed system circuits   Plan of attack based on traditional testing, circuit design and circuit manufacture allows the reader to appreciate a testing regime from the point of view of all the participating interests   Worked examples based on theoretical bookwork, practical experimentation and simulation exercises teach the reader how to test circuits thoroughly and effectively...read more