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Tables of Contents for Parallel Vlsi Neural System Design
Chapter/Section Title
Page #
Page Count
Preface
v
 
CHAPTER 1 VLSI Neural System Design Methodology
1
20
1.1 INTRODUCTION
1
2
1.2 NEURAL NETWORK MODELS
3
7
1.2.1 Biological Neural Networks
3
3
1.2.2 Artificial Neural Networks
6
4
1.3 ANN ARCHITECTURES
10
1
1.4 HARDWARE IMPLEMENTATIONS
11
3
1.4.1 Analog and Mixed Implementations
12
1
1.4.2 Digital Implementations
13
1
1.5 VLSI SYSTEM DESIGN METHODOLOGY
14
7
PART I PARALLEL ANN MODELS
21
50
CHAPTER 2 An Unsupervised Learning Model
23
18
2.1 INTRODUCTION
23
5
2.2 FUZZY CLUSTERING NEURAL NETWORKS
28
4
2.2.1 Network Architecture
28
1
2.2.2 Learning Algorithm
28
4
2.3 PARALLEL FCNN MODEL
32
1
2.4 EXPERIMENTAL RESULTS
32
8
2.5 SUMMARY
40
1
CHAPTER 3 A Supervised Training Model
41
18
3.1 INTRODUCTION
41
3
3.2 LINEAR SEPARABILITY ANALYSIS
44
4
3.2.1 Definitions
44
2
3.2.2 Layered Perceptrons
46
2
3.3 LAYER ADAPTATION APPROACH
48
5
3.3.1 Linear Separability Principle
49
1
3.3.2 Adaptation Approach
50
3
3.4 EXPERIMENT: PATTERN RECOGNITION
53
2
3.5 COMPARISONS
55
2
3.6 SUMMARY
57
2
CHAPTER 4 A Neural-Like Network Model
59
12
4.1 INTRODUCTION
59
4
4.1.1 Notation
60
1
4.1.2 Residue Number System (RNS)
61
1
4.1.3 Neural Network Architecture
61
2
4.2 FRNN COMPUTING MODEL
63
3
4.3 FRNN ARCHITECTURE
66
1
4.4 CASE STUDIES
67
3
4.4.1 A Multiplier
68
1
4.4.2 RNS to Binary Converter
69
1
4.5 SUMMARY
70
1
PART II VLSI ARCHITECTURES
71
78
CHAPTER 5 Mapping ANN onto Systolic Arrays
73
20
5.1 INTRODUCTION
73
6
5.1.1 Systolic Arrays
74
3
5.1.2 Mapping Algorithm to Systolic Architecture
77
2
5.2 MAPPING POLICIES
79
3
5.3 DESIGN APPROACH
82
4
5.3.1 Typical SA Structures
82
2
5.3.2 Pipeline Matching
84
1
5.3.3 Iteration Processing
84
2
5.4 CASE STUDY
86
5
5.4.1 Hamming Net
86
4
5.4.2 Simulations and Experiments
90
1
5.5 SUMMARY
91
2
CHAPTER 6 A Parallel Architecture Implemented by Systolic Arrays
93
14
6.1 INTRODUCTION
93
1
6.2 FCNN ARCHITECTURE
94
2
6.3 PERFORMANCE ANALYSIS
96
4
6.4 MAPPING FCNN ONTO SA
100
6
6.5 SUMMARY
106
1
CHAPTER 7 A Pipelined Architecture Based on Window Operation
107
24
7.1 INTRODUCTION
107
2
7.2 PIPELINED ARCHITECTURE
109
7
7.2.1 Window Model
109
2
7.2.2 Pipelined Architecture
111
1
7.2.3 Building Unit Design
112
4
7.3 WINDOW IMPLEMENTATION
116
4
7.3.1 Parallel Data Flow Window
116
1
7.3.2 Serial Data Flow Window
117
1
7.3.3 Window Computation Element
118
2
7.4 CASE STUDIES
120
6
7.5 PERFORMANCE ANALYSIS
126
3
7.6 SUMMARY
129
2
CHAPTER 8 A Simplified Architecture Using A Priori Knowledge
131
18
8.1 INTRODUCTION
131
2
8.2 TYPICAL STRUCTURE MODELS
133
3
8.2.1 Output ROM Model
133
2
8.2.2 Input ROM Model
135
1
8.2.3 Learning ROM Model
135
1
8.3 ROM LAYER IN VLSI
136
1
8.4 EXAMPLES
136
11
8.5 SUMMARY
147
2
PART III HARDWARE IMPLEMENTATIONS
149
86
CHAPTER 9 Computational Blocks Design for Digital ANN
151
22
9.1 INTRODUCTION
151
1
9.2 PIPELINED SWITCHING TREES
152
1
9.3 GRAPH BASED REDUCTION
153
8
9.3.1 Graph Reduction Rules
154
3
9.3.2 Minimization Considerations
157
2
9.3.3 Example Results
159
2
9.4 CIRCUIT CONSIDERATIONS
161
9
9.4.1 Worst Case Test
161
1
9.4.2 Reduction of Charge Sharing
162
3
9.4.3 Reduction of Tree Height
165
4
9.4.4 Transistor Sizing
169
1
9.5 PRELIMINARY FABRICATION RESULTS
170
1
9.6 SUMMARY
171
2
CHAPTER 10 Digital ANN Compressor Design
173
18
10.1 INTRODUCTION
173
2
10.2 C^2 PL MODEL
175
1
10.3 3-2 COMPRESSOR DESIGN
176
7
10.3.1 Basic Structure
177
4
10.3.2 Comparison with CPL
181
2
10.4 DNN APPLICATIONS
183
6
10.5 SUMMARY
189
2
CHAPTER 11 Hybrid Programmable ANN Design
191
16
11.1 INTRODUCTION
191
2
11.2 ANALYSIS AND DESIGN FOR PRNN
193
4
11.3 IMPROVED PRNN CIRCUIT
197
4
11.3.1 Synapse Building Block
197
2
11.3.2 Neuron Building Block
199
2
11.3.3 Connection Network
201
1
11.4 EXPERIMENTAL RESULTS
201
2
11.5 SUMMARY
203
1
APPENDIX A
203
4
CHAPTER 12 VLSI Implementation for Finite Ring ANN
207
20
12.1 INTRODUCTION
207
1
12.2 FRRR Architecture
208
5
12.2.1 Modulo Reduction
208
1
12.2.2 MSB Carry Iteration
209
3
12.2.3 Feedforward Processing
212
1
12.3 VLSI IMPLEMENTATION
213
5
12.3.1 Carry Look-Ahead Adder
214
2
12.3.2 ROM Implementation
216
1
12.3.3 ROM Logic Cell
217
1
12.4 COMPARISON
218
5
12.5 SUMMARY
223
2
APPENDIX B
225
2
CHAPTER 13 Conclusions and Prospects
227
8
Bibliography
235
18
Index
253