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Tables of Contents for Soc (System-On-A-Chip) Testing for Plug and Play Test Automation
Chapter/Section Title
Page #
Page Count
Foreword
v
V.D. Agrawal
Preface
vii
K. Chakrabarty
Overview
On IEEE P1500's Standard for Embedded Core Test
1
20
E.J. Marinissen
R. Kapur
M. Lousberg
T. Mclaurin
M. Ricchetti
Y. Zorian
Test Planning, Access and Scheduling
An Integrated Framework for the Design and Optimization of SOC Test Solutions
21
16
E. Larsson
Z. Peng
On Concurrent Test of Core-Based SOC Design
37
14
Y. Huang
W.-T. Cheng
C.-C. Tsai
N. Mukherjee
O. Samman
Y. Zaidan
S.M. Reddy
A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based Socs and its Associated Scheduling Algorithm
51
20
S. Koranne
The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System Ics
71
20
E.J. Marinissen
Cas-Bus: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
91
20
M. Benabdenbi
W. Maroufi
M. Marzouki
An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch
111
12
S. Basu
I. Sengupta
D.R. Chowdhury
S. Bhawmik
Design for Consecutive Testability of System-On-a-Chip with Built-In Self Testable Cores
123
16
T. Yoneda
H. Fujiwara
Test Data Compression
Deterministic Test Vector Compression/Decompression for Systems-On-a-Chip Using an Embedded Processor
139
12
A. Jas
N.A. Touba
Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test
151
14
J.-F. Li
R.-S. Tzeng
C.-W. Wu
Interconnect, Crosstalk and Signal Integrity
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
165
10
L. Chen
X. Bai
S. Dey
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
175
16
M. Nourani
A. Attarha
On-Chip Clock Faults' Detector
191
C. Metra
M. Favalli
S. Di Francescantonio
B. Ricco