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Tables of Contents for Timing Verification of Application-Specific Integrated Circuits
Chapter/Section Title
Page #
Page Count
List of Figures
xi
 
List of Tables
xv
 
Preface
xvii
 
Acknowledgments
xix
 
Introduction to Timing Verification
1
16
Introduction
1
1
Overview of Timing Verification
2
9
Intrinsic vs. Extrinsic Delay
4
3
Path Delay
7
4
Interface Timing Analysis
11
6
Elements of Timing Verification
17
28
Introduction
17
1
Clock Definitions
17
11
Gated Clocks
19
3
Clock Skews and Multiple Clock Groups
22
3
Multifrequency Clocks
25
1
Multiphase Clocks
26
2
More on STA
28
10
False Paths
28
2
Multicycle Path Analysis
30
1
Timing Specifications
31
4
Timing Checks
35
3
Timing Analysis of Phase-Locked Loops
38
7
PLL Basics
38
1
PLL Ideal Behavior
39
2
PLL Errors
41
4
Timing in ASICs
45
54
Introduction
45
3
Prelayout Timing
48
35
RTL vs. Gate-Level Timing
49
1
Timing in RTL Code
50
3
Delay with a Continuous Assignment Statement
53
1
Delay in a Process Statement
54
2
Intra-Assignment Delays
56
2
The Verilog Specify Block
58
6
Timing in-Gate Level Code
64
1
Synthesis and Timing Constraints
64
1
Design Rule Constraints
65
1
Optimization Constraints
66
3
Gate and Wire-Load Models
69
3
The Synthesis Flow
72
9
Synthesis Tips
81
1
Back Annotation to Gate-Level RTL
82
1
Postlayout Timing
83
10
Manual Line-Propagation Delay Calculations
83
1
Signal-Line Capacitance Calculation
84
6
Signal Line Resistance Calculation
90
2
Signal Trace RC Delay Evaluation
92
1
ASIC Sign-Off Checklist
93
6
Library Development
94
1
Functional Specification
94
1
RTL Coding
94
1
Simulations of RTL
95
1
Logic Synthesis
95
1
Test Insertion and ATPG
95
1
Postsynthesis Gate-Level Simulation or Static Timing Analysis
95
1
Floorplanning
96
1
Place and Route
96
1
Final Verification of the Extracted Netlist
96
1
Mask Generation and Fabrication
97
1
Testing
97
2
Programmable Logic Based Design
99
52
Introduction
99
2
Programmable Logic Structures
101
7
Logic Block
105
1
Input/Output Block
106
1
Routing Facilities
106
2
Design Flow
108
3
Timing Parameters
111
5
Timing Derating Factors
112
2
Grading Programmable Logic Devices by Speed
114
1
Best-Case Delay Values
115
1
Timing Analysis
116
21
Actel ACT FPGA Family
117
1
Actel ACT 3 Architecture
117
1
Actel ACT 3 Timing Model
118
4
Altera FLEX 8000
122
1
Altera FLEX 8000 Architecture
122
1
Altera FLEX 8000 Timing Model
123
5
Xilinx XC3000 /XC4000 FPGA Families
128
2
Xilinx XC9500 CPLD
130
1
Xilinx XC9500 CPLD Architecture
131
2
Xilinx XC9500 CPLD Timing Model
133
4
HDL Synthesis
137
2
Software Development Systems
139
12
Timing Constraints
140
2
Operating Conditions
142
1
Static Timing Analysis
142
1
Vendor-Specific Timing-Verification Tools
143
1
Actel Designer
144
2
Altera MAX+PLUS II
146
1
Xilinx XACT/M1
147
4
A Prime Time
151
6
B Pearl
157
4
C TimingDesigner
161
2
D Transistor-Level Timing Verification
163
6
References
169
4
Index
173
12
About the Author
185