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Tables of Contents for Digital Principles and Design
Chapter/Section Title
Page #
Page Count
Preface
xiii
Introduction
1
6
The Digital Age
1
1
Analog and Digital Representations of Information
2
1
The Digital Computer
2
3
The Organization of a Digital Computer
3
2
The Operation of a Digital Computer
5
1
An Overview
5
2
Number Systems, Arithmetic, and Codes
7
54
Positional Number Systems
7
2
Counting in a Positional Number System
9
2
Basic Arithmetic Operations
11
5
Addition
11
1
Subtraction
11
3
Multiplication
14
2
Division
16
1
Polynomial Method of Number Conversion
16
3
Iterative Method of Number Conversion
19
5
Iterative Method for Converting Integers
20
1
Verification of the Iterative Method for Integers
21
1
Iterative Method for Converting Fractions
22
1
Verification of the Iterative Method for Fractions
23
1
A Final Example
23
1
Special Conversion Procedures
24
2
Signed Numbers and Complements
26
5
Addition and Subtraction with r's-Complements
31
5
Signed Addition and Subtraction
33
3
Addition and Subtraction with (r - 1)'s-Complements
36
5
Signed Addition and Subtraction
39
2
Codes
41
7
Decimal Codes
41
3
Unit-Distance Codes
44
2
Alphanumeric Codes
46
2
Error Detection
48
2
Error Correction
50
11
Hamming Code
51
3
Single-Error Correction plus Double-Error Detection
54
1
Check Sum Digits for Error Correction
54
1
Problems
55
6
Boolean Algebra and Combinational Networks
61
66
Definition of a Boolean Algebra
62
1
Principle of Duality
63
1
Boolean Algebra Theorems
63
7
A Two-Valued Boolean Algebra
70
3
Boolean Formulas and Functions
73
3
Normal Formulas
75
1
Canonical Formulas
76
7
Minterm Canonical Formulas
76
2
m-Notation
78
2
Maxterm Canonical Formulas
80
1
M-Notation
81
2
Manipulations of Boolean Formulas
83
8
Equation Complementation
83
1
Expansion about a Variable
84
1
Equation Simplification
84
2
The Reduction Theorems
86
1
Minterm Canonical Formulas
87
1
Maxterm Canonical Formulas
88
1
Complements of Canonical Formulas
89
2
Gates and Combinational Networks
91
6
Gates
92
1
Combinational Networks
92
1
Analysis Procedure
93
1
Synthesis Procedure
94
1
A Logic Design Example
95
2
Incomplete Boolean Functions and Don't-Care Conditions
97
4
Describing Incomplete Boolean Functions
99
1
Don't-Care Conditions in Logic Design
99
2
Additional Boolean Operations and Gates
101
12
The Nand-Function
102
1
The Nor-Function
103
1
Universal Gates
103
2
Nand-Gate Realizations
105
3
Nor-Gate Realizations
108
3
The Exclusive-Or-Function
111
2
The Exclusive-Nor-Function
113
1
Gate Properties
113
14
Noise Margins
115
1
Fan-Out
116
1
Propagation Delays
117
1
Power Dissipation
118
1
Problems
118
9
Simplification of Boolean Expressions
127
103
Formulation of the Simplification Problem
127
2
Criteria of Minimality
128
1
The Simplification Problem
129
1
Prime Implicants and Irredundant Disjunctive Expressions
129
4
Implies
129
1
Subsumes
130
1
Implicants and Prime Implicants
131
2
Irredundant Disjunctive Normal Formulas
133
1
Prime Implicates and Irredundant Conjunctive Expressions
133
2
Karnaugh Maps
135
10
One-Variable and Two-Variable Maps
135
1
Three-Variable and Four-Variable Maps
136
2
Karnaugh Maps and Canonical Formulas
138
3
Product and Sum Term Representations on Karnaugh Maps
141
4
Using Karnaugh Maps to Obtain Minimal Expressions for Complete Boolean Functions
145
12
Prime Implicants and Karnaugh Maps
145
5
Essential Prime Implicants
150
1
Minimal Sums
151
4
Minimal Products
155
2
Minimal Expressions of Incomplete Boolean Functions
157
3
Minimal Sums
158
1
Minimal Products
159
1
Five-Variable and Six-Variable Karnaugh Maps
160
6
Five-Variable Maps
160
3
Six-Variable Maps
163
3
The Quine-McCluskey Method of Generating Prime Implicants and Prime Implicates
166
8
Prime Implicants and the Quine-McCluskey Method
167
3
Algorithm for Generating Prime Implicants
170
3
Prime Implicates and the Quine-McCluskey Method
173
1
Prime-Implicant/Prime-Implicate Tables and Irredundant Expressions
174
4
Petrick's Method of Determining Irredundant Expressions
175
3
Prime-Implicate Tables and Irredundant Conjunctive Normal Formulas
178
1
Prime-Implicant/Prime-Implicate Table Reductions
178
6
Essential Prime Implicants
179
1
Column and Row Reductions
180
4
A Prime-Implicant Selection Procedure
184
1
Decimal Method for Obtaining Prime Implicants
184
3
The Multiple-Output Simplification Problem
187
4
Multiple-Output Prime Implicants
191
1
Obtaining Multiple-Output Minimal Sums and Products
191
11
Tagged Product Terms
192
1
Generating the Multiple-Output Prime Implicants
193
2
Multiple-Output Prime-Implicant Tables
195
1
Minimal Sums Using Petrick's Method
196
2
Minimal Sums Using Table Reduction Techniques
198
3
Multiple-Output Minimal Products
201
1
Variable-Entered Karnaugh Maps
202
28
Constructing Variable-Entered Maps
203
4
Reading Variable-Entered Maps for Minimal Sums
207
5
Minimal Products
212
1
Incompletely Specified Functions
213
5
Maps Whose Entries Are Not Single-Variable Functions
218
4
Problems
222
8
Logic Design with MSI Components and Programmable Logic Devices
230
71
Binary Adders and Subtracters
231
11
Binary Subtracters
233
3
Carry Lookahead Adder
236
2
Large High-Speed Adders Using the Carry Lookahead Principle
238
4
Decimal Adders
242
4
Comparators
246
2
Decoders
248
12
Logic Design Using Decoders
249
7
Decoders with an Enable Input
256
4
Encoders
260
2
Multiplexers
262
14
Logic Design with Multiplexers
266
10
Programmable Logic Devices (PLDs)
276
3
PLD Notation
279
1
Programmable Read-Only Memories (PROMs)
279
4
Programmable Logic Arrays (PLAs)
283
9
Programmable Array Logic (PAL) Devices
292
9
Problems
294
7
Flip-Flops and Simple Flip-Flop Applications
301
66
The Basic Bistable Element
302
1
Latches
303
7
The SR Latch
304
1
An Application of the SR Latch: A Switch Debouncer
305
2
The SR Latch
307
1
The Gated SR Latch
308
1
The Gated D Latch
309
1
Timing Considerations
310
3
Propagation Delays
310
2
Minimum Pulse Width
312
1
Setup and Hold Times
312
1
Master-Slave Flip-Flops (Pulse-Triggered Flip-Flops)
313
8
The Master-Slave SR Flip-Flop
314
3
The Master-Slave JK Flip-Flop
317
2
0's and 1's Catching
319
1
Additional Types of Master-Slave Flip-Flops
320
1
Edge-Triggered Flip-Flops
321
8
The Positive-Edge-Triggered D Flip-Flop
321
3
Negative-Edge-Triggered D Flip-Flops
324
1
Asynchronous Inputs
324
2
Additional Types of Edge-Triggered Flip-Flops
326
2
Master-Slave Flip-Flops with Data Lockout
328
1
Characteristic Equations
329
3
Registers
332
5
Counters
337
10
Binary Ripple Counters
337
3
Synchronous Binary Counters
340
5
Counters Based on Shift Registers
345
2
Design of Synchronous Counters
347
20
Design of a Synchronous Mod-6 Counter Using Clocked JK Flip-Flops
348
4
Design of a Synchronous Mod-6 Counter Using Clocked D, T, or SR Flip-Flops
352
4
Self-Correcting Counters
356
2
Problems
358
9
Synchronous Sequential Networks
367
77
Structure and Operation of Clocked Synchronous Sequential Networks
368
3
Analysis of Clocked Synchronous Sequential Networks
371
14
Excitation and Output Expressions
373
1
Transition Equations
374
1
Transition Tables
375
2
Excitation Tables
377
2
State Tables
379
1
State Diagrams
380
2
Network Terminal Behavior
382
3
Modeling Clocked Synchronous Sequential Network Behavior
385
13
The Serial Binary Adder as a Mealy Network
385
3
The Serial Binary Adder as a Moore Network
388
2
A Sequence Recognizer
390
3
A 0110/1001 Sequence Recognizer
393
3
A Final Example
396
2
State Table Reduction
398
17
Determining Equivalent Pairs of States
399
6
Obtaining the Equivalence Classes of States
405
1
Constructing the Minimal State Table
406
4
The 0110/1001 Sequence Recognizer
410
5
The State Assignment
415
9
Some Simple Guidelines for Obtaining State Assignments
418
4
Unused States
422
2
Completing the Design of Clocked Synchronous Sequential Networks
424
20
Realizations Using Programmable Logic Devices
432
4
Problems
436
8
Algorithmic State Machines
444
61
The Algorithmic State Machine
444
3
ASM Charts
447
14
The State Box
448
1
The Decision Box
449
1
The Conditional Output Box
450
1
ASM Blocks
450
6
ASM Charts
456
3
Relationship between State Diagrams and ASM Charts
459
2
Two Examples of Synchronous Sequential Network Design Using ASM Charts
461
7
A Sequence Recognizer
461
2
A Parallel (Unsigned) Binary Multiplier
463
5
State Assignments
468
2
ASM Tables
470
9
ASM Transition Tables
470
2
Assigned ASM Transition Tables
472
3
Algebraic Representation of Assigned Transition Tables
475
2
ASM Excitation Tables
477
2
ASM Realizations
479
12
Realizations Using Discrete Gates
479
5
Realizations Using Multiplexers
484
3
Realizations Using PLAs
487
3
Realizations Using PROMs
490
1
Asynchronous Inputs
491
14
Problems
493
12
Asynchronous Sequential Networks
505
84
Structure and Operation of Asynchronous Sequential Networks
506
4
Analysis of Asynchronous Sequential Networks
510
10
The Excitation Table
512
2
The Transition Table
514
2
The State Table
516
1
The Flow Table
517
2
The Flow Diagram
519
1
Races in Asynchronous Sequential Networks
520
2
The Primitive Flow Table
522
7
The Primitive Flow Table for Example 9.3
523
3
The Primitive Flow Table for Example 9.4
526
3
Reduction of Input-Restricted Flow Tables
529
9
Determination of Compatible Pairs of States
530
3
Determination of Maximal Compatibles
533
2
Determination of Minimal Collections of Maximal Compatible Sets
535
1
Constructing the Minimal-Row Flow Table
536
2
A General Procedure to Flow Table Reduction
538
7
Reducing the Number of Stable States
538
2
Merging the Rows of a Primitive Flow Table
540
3
The General Procedure Applied to Input-Restricted Primitive Flow Tables
543
2
The State-Assignment Problem and the Transition Table
545
12
The Transition Table for Example 9.3
546
4
The Transition Table for Example 9.4
550
1
The Need for Additional State Variables
551
4
A Systematic State-Assignment Procedure
555
2
Completing the Asynchronous Sequential Network Design
557
4
Static and Dynamic Hazards in Combinational Networks
561
12
Static Hazards
562
3
Detecting Static Hazards
565
3
Eliminating Static Hazards
568
2
Dynamic Hazards
570
1
Hazard-Free Combinational Logic Networks
571
1
Hazards in Asynchronous Networks Involving Latches
571
2
Essential Hazards
573
16
Example of an Essential Hazard
574
1
Detection of Essential Hazards
575
3
Problems
578
11
Appendix A Digital Circuits
589
76
A.1 The pn Junction Semiconductor Diode
590
3
A.1.1 Semiconductor Diode Behavior
590
2
A.1.2 Semiconductor Diode Models
592
1
A.2 Diode Logic
593
4
A.2.1 The Diode And-Gate
594
1
A.2.2 The Diode Or-Gate
595
1
A.2.3 Negative Logic
596
1
A.3 The Bipolar Junction Transistor
597
11
A.3.1 Simplified de Transistor Operation
598
2
A.3.2 Normal Active Mode
600
2
A.3.3 Inverted Active Mode
602
1
A.3.4 Cutoff Mode
603
2
A.3.5 Saturation Mode
605
1
A.3.6 Silicon npn Transistor Characteristics
606
2
A.3.7 Summary
608
1
A.4 The Transistor Inverter
608
6
A.4.1 Loading Effects
611
3
A.5 Gate Performance Considerations
614
4
A.5.1 Noise Margins
614
2
A.5.2 Fan-Out
616
1
A.5.3 Speed of Operation and Propagation Delay Times
616
2
A.5.4 Power Dissipation
618
1
A.6 Diode-Transistor Logic (DTL)
618
4
A.6.1 Loading Effects
620
1
A.6.2 Modified DTL
621
1
A.7 Transistor-Transistor Logic (TTL)
622
12
A.7.1 Wired Logic
625
1
A.7.2 TTL with Totem-Pole Output
626
4
A.7.3 Three-State Output TTL
630
2
A.7.4 Schottky TTL
632
2
A.7.5 Concluding Remarks
634
1
A.8 Emitter-Coupled Logic (ECL)
634
7
A.8.1 The Current Switch
635
3
A.8.2 The Emitter-Follower Level Restorers
638
1
A.8.3 The Reference Supply
639
1
A.8.4 Wired Logic
639
2
A.9 The MOS Field-Effect Transistor
641
8
A.9.1 Operation of the n-Channel, Enhancement-Type MOSFET
641
4
A.9.2 The n-Channel, Depletion-Type MOSFET
645
1
A.9.3 The p-Channel MOSFETs
646
1
A.9.4 Circuit Symbols
646
1
A.9.5 The MOSFET as a Resistor
647
1
A.9.6 Concluding Remarks
648
1
A.10 NMOS and PMOS Logic
649
5
A.10.1 The NMOS Inverter (Not-Gate)
649
1
A.10.2 NMOS Nor-Gate
650
1
A.10.3 NMOS Nand-Gate
651
1
A.10.4 PMOS Logic
652
1
A.10.5 Performance
652
2
A.11 CMOS Logic
654
11
A.11.1 The CMOS Inverter (Not-Gate)
654
1
A.11.2 CMOS Nor-Gate
655
1
A.11.3 CMOS Nand-Gate
656
1
A.11.4 Performance
657
1
Problems
657
8
Appendix B Tutorials
665
19
B.1 A Gentle Introduction to Altera MAX+plus II 10.1 Student Edition
665
13
B.2 A Gentle Introduction to LogicWorks™4
678
6
Bibliography
684
3
Index
687