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SystemVerilog for Verification: A Guide to Learning the Testbench Language Features
By
Chris Spear and
Greg Tumbush
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Bibliographic Detail
Publisher
Springer-Verlag New York Inc
Publication date
February 14, 2012
Pages
464
Binding
Hardcover
Edition
3
Book category
Adult Non-Fiction
ISBN-13
9781461407140
ISBN-10
1461407141
Dimensions
1 by 6 by 9 in.
Weight
1.85 lbs.
Original list price
$99.00
Amazon.com says people who bought this book also bought:
Cracking Digital VLSI Verification Interview: Interview Success | Logic Design and Verification Using SystemVerilog (Revised) | RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design | A Practical Guide to Adopting the Universal Verification Methodology (Uvm) Second Edition | The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology | Systemverilog for Design | Digital Logic Rtl & Verilog Interview Questions
Cracking Digital VLSI Verification Interview: Interview Success | Logic Design and Verification Using SystemVerilog (Revised) | RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design | A Practical Guide to Adopting the Universal Verification Methodology (Uvm) Second Edition | The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology | Systemverilog for Design | Digital Logic Rtl & Verilog Interview Questions
Summaries and Reviews
Editions
Hardcover
The price comparison is for this edition
With Greg Tumbush |
3 edition from Springer-Verlag New York Inc (February 14, 2012)
9781461407140 | details & prices | 464 pages | 6.00 × 9.00 × 1.00 in. | 1.85 lbs | List price $99.00
from Springer-Verlag New York Inc (August 30, 2006)
9780387270364 | details & prices | 301 pages | 6.00 × 9.25 × 0.75 in. | 1.50 lbs | List price $135.00
About: SystemVerilog for Verification teaches the reader how to use the power of the new SystemVerilog testbench constructs plus methodology without requiring in-depth knowledge of Object Oriented Programming or Constrained Random Testing.
About: SystemVerilog for Verification teaches the reader how to use the power of the new SystemVerilog testbench constructs plus methodology without requiring in-depth knowledge of Object Oriented Programming or Constrained Random Testing.
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