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Tables of Contents for See Mips Run
Chapter/Section Title
Page #
Page Count
Foreword
v
10
Preface
xv
Style and Limits
xvii
1
Conventions
xviii
1
Acknowledgments
xviii
Chapter 1 RISCs and MIPS
1
18
1.1 Pipelines
2
3
1.1.1 What Makes a Pipeline Inefficient?
3
1
1.1.2 The Pipeline and Caching
4
1
1.2 The MIPS Five-Stage Pipeline
5
2
1.3 RISC and CISC
7
1
1.4 Great MIPS Chips of the Past and Present
7
5
1.4.1 R2000 to R3000
7
1
1.4.2 R6000: A Diversion
8
1
1.4.3 The R4000 Revolution
9
1
1.4.4 R5000 and R10000
9
3
1.5 MIPS Compared with CISC Architectures
12
7
1.5.1 Constraints on MIPS Instructions
12
1
1.5.2 Addressing and Memory Accesses
13
1
1.5.3 Features You Won't Find
14
2
1.5.4 A Feature You Might Not Expect
16
1
1.5.5 Programmer-Visible Pipeline Effects
16
3
Chapter 2 MIPS Architecture
19
24
2.1 A Flavor of MIPS Assembly Language
20
1
2.2 Registers
21
4
2.2.1 Conventional Names and Uses of General-Purpose Registers
22
3
2.3 Integer Multiply Unit and Registers
25
1
2.4 Loading and Storing: Addressing Modes
26
1
2.5 Data Types in Memory and Registers
27
2
2.5.1 Integer Data Types
27
1
2.5.2 Unaligned Loads and Stores
28
1
2.5.3 Floating-Point Data in Memory
29
1
2.6 Synthesized Instructions in Assembly Language
29
2
2.7 MIPS I to MIPS IV: 64-Bit (and Other) Extensions
31
5
2.7.1 To 64 Bits
32
1
2.7.2 Who Needs 64 Bits?
33
1
2.7.3 Regarding 64 Bits and No Mode Switch: Data in Registers
34
1
2.7.4 Other Innovations in MIPS III
35
1
2.8 Basic Address Space
36
3
2.8.1 Addressing in Simple Systems
38
1
2.8.2 Kernel vs. User Privilege Level
38
1
2.8.3 The Full Picture: The 64-Bit View of the Memory Map
39
1
2.9 Pipeline Hazards
39
4
Chapter 3 Coprocessor O: MIPS Processor Control
43
20
3.1 CPU Control Instructions
46
1
3.2 What Registers Are Relevant When?
47
1
3.3 Encodings of Standard CPU Control Registers
48
10
3.3.1 Processor ID (PRId) Register
49
1
3.3.2 Status Register (SR)
50
5
3.3.3 Cause Register
55
1
3.3.4 Exception Return Address (EPC) Register
56
1
3.3.5 Bad Virtual Address (BadVaddr) Register
56
2
3.4 Control Registers for the R4000 CPU and Followers
58
5
3.4.1 Count/Compare Registers: The R4000 Timer
58
1
3.4.2 Config Register: R4x00 Configuration
59
3
3.4.3 Load-Linked Address (LLAddr) Register
62
1
3.4.4 Debugger Watchpoint (WatchLo/WatchHi) Registers
62
1
Chapter 4 Caches for MIPS
63
28
4.1 Caches and Cache Management
63
1
4.2 How Caches Work
64
2
4.3 Write-Through Caches in Early MIPS CPUs
66
1
4.4 Write-Back Caches in Recent MIPS CPUs
67
1
4.5 Other Choices in Cache Design
68
1
4.6 Managing Caches
69
2
4.7 Secondary and Tertiary Caches
71
1
4.8 Cache Configurations for MIPS CPUs
71
2
4.9 Programming R3000-Style Caches
73
3
4.9.1 Using Cache Isolation and Swapping
74
1
4.9.2 Initializing and Sizing
75
1
4.9.3 Invalidation
75
1
4.9.4 Testing and Probing
76
1
4.10 Programming R4000-Style Caches
76
7
4.10.1 CacheERR, ERR, and ErrorEPC Registers: Cache Error Handling
78
1
4.10.2 The Cache Instruction
79
2
4.10.3 Cache Sizing and Figuring Out Configuration
81
1
4.10.4 Initialization Routines
81
2
4.10.5 Invalidating or Writing Back a Region of Memory in the Cache
83
1
4.11 Cache Efficiency
83
2
4.12 Reorganizing Software to Influence Cache Efficiency
85
2
4.13 Write Buffers and When You Need to Worry
87
3
4.13.1 Implementing wbflush
89
1
4.14 More about MIPS Caches
90
1
4.14.1 Multiprocessor Cache Features
90
1
4.14.2 Cache Aliases
90
1
Chapter 5 Exceptions, Interrupts, and Initialization
91
24
5.1 Precise Exceptions
93
1
5.2 When Exceptions Happen
94
1
5.3 Exception Vectors: Where Exception Handling Starts
95
4
5.4 Exception Handling: Basics
99
1
5.5 Returning from an Exception
100
1
5.6 Nesting Exceptions
100
1
5.7 An Exception Routine
101
1
5.8 Interrupts
101
8
5.8.1 Interrupt Resources in MIPS CPUs
102
2
5.8.2 Implementing Interrupt Priority
104
2
5.8.3 Atomicity and Atomic Changes to SR
106
1
5.8.4 Critical Regions with Interrupts Enabled: Semaphores the MIPS Way
107
2
5.9 Starting Up
109
4
5.9.1 Probing and Recognizing Your CPU
111
1
5.9.2 Bootstrap Sequences
112
1
5.9.3 Starting Up an Application
113
1
5.10 Emulating Instructions
113
2
Chapter 6 Memory Management and the TLB
115
34
6.1 Memory Management in Big Computers
117
6
6.1.1 Basic Process Layout and Protection
117
2
6.1.2 Mapping Process Addresses to Real Memory
119
1
6.1.3 Paged Mapping Preferred
120
1
6.1.4 What We Really Want
121
2
6.1.5 Origins of the MIPS Design
123
1
6.2 MIPS TLB Facts and Figures
123
3
6.3 MMU Registers Described
126
7
6.3.1 EntryHi, EntryLo, and PageMask
127
4
6.3.2 Index
131
1
6.3.3 Random
131
1
6.3.4 Wired
132
1
6.3.5 Context and XContext
132
1
6.4 MMU Control Instructions
133
1
6.5 Programming the TLB
134
2
6.5.1 How Refill Happens
134
1
6.5.2 Using ASIDs
135
1
6.5.3 The Random Register and Wired Entries
136
1
6.6 Memory Translation: Setup
136
2
6.7 TLB Exception Sample Code
138
7
6.7.1 The 32-Bit R3000-Style User TLB Miss Exception Handler
139
2
6.7.2 TLB Miss Exception Handler for R4x00 CPU
141
3
6.7.3 XTLB Miss Handler
144
1
6.8 Keeping Track of Modified Pages (Simulating "Dirty" Bits)
145
1
6.9 Memory Translation and 64-Bit Pointers
145
1
6.10 Everyday Use of the MIPS TLB
146
1
6.11 Memory Management in a Non-unix OS
147
2
Chapter 7 Floating-Point Support
149
26
7.1 A Basic Description of Floating Point
149
1
7.2 The IEEE754 Standard and Its Background
150
2
7.3 How IEEE Floating-Point Numbers Are Stored
152
4
7.3.1 IEEE Mantissa and Normalization
153
1
7.3.2 Reserved Exponent Values for Use with Strange Values
153
1
7.3.3 MIPS FP Data Formats
154
2
7.4 MIPS Implementation of IEEE754
156
1
7.4.1 Need for FP Trap Handler and Emulator in All MIPS CPUs
157
1
7.5 Floating-Point Registers
157
1
7.5.1 Conventional Names and Uses of Floating-Point Registers
158
1
7.6 Floating-Point Exceptions/Interrupts
158
1
7.7 Floating-Point Control: The Control/Status Register
159
3
7.8 Floating-Point Implementation/Revision Register
162
1
7.9 Guide to FP Instructions
163
7
7.9.1 Load/Store
164
1
7.9.2 Move between Registers
165
1
7.9.3 Three-Operand Arithmetic Operations
166
1
7.9.4 Multiply-Add Operations
166
1
7.9.5 Unary (Sign-Changing) Operations
167
1
7.9.6 Conversion Operations
167
1
7.9.7 Conditional Branch and Test Instructions
168
2
7.10 Instruction Timing Requirements
170
1
7.11 Instruction Timing for Speed
171
1
7.12 Initialization and Enabling on Demand
172
1
7.13 Floating-Point Emulation
172
3
Chapter 8 Complete Guide to the MIPS Instruction Set
175
68
8.1 A Simple Example
175
2
8.2 Assembler Mnemonics and What They Mean
177
24
8.2.1 U and Non-U Mnemonics
178
1
8.2.2 Divide Mnemonics
179
1
8.2.3 Inventory of Instructions
180
1
8.3 Floating-Point Instructions
201
1
8.4 Peculiar Instructions and Their Purposes
202
15
8.4.1 Load Left/Load Right: Unaligned Load and Store
206
4
8.4.2 Load-Linked/Store-Conditional
210
1
8.4.3 Conditional Move Instructions
211
1
8.4.4 Branch-Likely
212
1
8.4.5 Integer Multiply-Accumulate and Multiply-Add Instructions
213
1
8.4.6 Floating-Point Multiply-Add Instructions
214
1
8.4.7 Multiple FP Condition Bits
215
1
8.4.8 Prefetch
215
1
8.4.9 Sync: A Load/Store Barrier
216
1
8.5 Instruction Encodings
217
14
8.5.1 Fields in the Instruction Encoding Table
217
2
8.5.2 Notes on the Instruction Encoding Table
219
12
8.5.3 Encodings and Simple Implementation
231
1
8.6 Instructions by Functional Group
231
12
8.6.1 Nop
231
1
8.6.2 Register/Register Moves
232
1
8.6.3 Load Constant
232
1
8.6.4 Arithmetical/Logical
232
2
8.6.5 Integer Multiply, Divide, and Remainder
234
2
8.6.6 Integer Multiply-Accumulate
236
1
8.6.7 Loads and Stores
237
2
8.6.8 Jumps, Subroutine Calls, and Branches
239
1
8.6.9 Breakpoint and Trap
240
1
8.6.10 CPO Functions
240
1
8.6.11 Floating Point
241
1
8.6.12 ATMizer-II Floating Point
242
1
Chapter 9 Assembler Language Programming
243
24
9.1 A Simple Example
243
4
9.2 Syntax Overview
247
1
9.2.1 Layout, Delimiters, and Identifiers
247
1
9.3 General Rules for Instructions
248
2
9.3.1 Computational Instructions: Three-, Two-, and One-Register
248
1
9.3.2 Immediates: Computational Instructions with Constants
249
1
9.3.3 Regarding 64-Bit and 32-Bit Instructions
250
1
9.4 Addressing Modes
250
3
9.4.1 Gp-Relative Addressing
251
2
9.5 Assembler Directives
253
14
9.5.1 Selecting Sections
253
2
9.5.2 Practical Program Layout Including Stack and Heap
255
1
9.5.3 Data Definition and Alignment
256
2
9.5.4 Symbol-Binding Attributes
258
2
9.5.5 Function Directives
260
2
9.5.6 Assembler Control (.set)
262
3
9.5.7 Compiler/Debugger Support
265
1
9.5.8 Additional Directives in SGI Assembly Language
265
2
Chapter 10 C Programming on MIPS
267
34
10.1 The Stack, Subroutine Linkage, and Parameter Passing
268
1
10.2 Stack Argument Structure
269
1
10.3 Using Registers to Pass Arguments
269
2
10.4 Examples from the C Library
271
1
10.5 An Exotic Example: Passing Structures
271
2
10.6 Passing a Variable Number of Arguments
273
1
10.7 Returning a Value from a Function
274
1
10.8 Evolving Register-Use Standards: SGI's n32 and n64
274
4
10.9 Stack Layouts, Stack Frames, and Helping Debuggers
278
10
10.9.1 Leaf Functions
280
1
10.9.2 Nonleaf Functions
281
3
10.9.3 Frame Pointers for More Complex Stack Requirements
284
4
10.10 Variable Number of Arguments and stdargs
288
1
10.11 Sharing Functions between Different Threads and Shared Library Problems
289
4
10.11.1 Sharing Code in Single-Address-Space Systems
290
1
10.11.2 Sharing Library Code in the MIPS ABI
290
3
10.12 An Introduction to Compiler Optimization
293
5
10.12.1 Common Optimizations
293
4
10.12.2 Optimizer-Unfriendly Code and How to Avoid It
297
1
10.12.3 The Limits of Optimization
297
1
10.13 Hints about Device Access from C
298
3
10.13.1 Using "volatile" to Inhibit Destructive Optimization
298
2
10.13.2 Unaligned Data from C
300
1
Chapter 11 Portability Considerations and C Code
301
32
11.1 Porting to MIPS: A Checklist of Frequently Encountered Problems
302
2
11.2 An Idealized Porting Process
304
3
11.2.1 Three Porting Choices
305
1
11.2.2 Fixing Up Dependencies
306
1
11.2.3 Isolating Nonportable Code
306
1
11.2.4 When to Use Assembler
306
1
11.3 Portable C and Language Standards
307
2
11.4 C Library Functions and POSIX
309
1
11.5 Data Representations and Alignment
309
3
11.6 Endianness: Words, Bytes, and Bit Order
312
15
11.6.1 Endianness and the Programmer
314
1
11.6.2 Endianness: The Pictures and the Intellectual Problem
315
2
11.6.3 Endianness: The Hardware Problem
317
3
11.6.4 Wiring a Connection between Opposite-Endian Camps
320
1
11.6.5 Wiring an Endianness-Configurable Connection
320
2
11.6.6 Software to Cope with Both-Endianness of a MIPS CPU
322
3
11.6.7 Portability and Endianness-Independent Code
325
1
11.6.8 Endianness and Foreign Data
325
1
11.6.9 False Cures and False Prophets for Endianness Problems
326
1
11.7 What Can Go Wrong with Caches and How to Stop It
327
3
11.7.1 Cache Management and DMA Data
328
1
11.7.2 Cache Management and Writing Instructions
329
1
11.7.3 Cache Management and Uncached/Write-Through Data
329
1
11.8 Different Implementations of MIPS
330
3
Chapter 12 Software Examples
333
62
12.1 Starting Up MIPS
333
11
12.2 MIPS Cache Management
344
25
12.2.1 Cache Operations: 32-Bit MIPS before Cache Instructions
345
9
12.2.2 Cache Operations: After MIPS III and Cache Instructions
354
15
12.3 MIPS Exception Handling
369
17
12.3.1 Xcption: What It Does for Programmers
369
1
12.3.2 Xcption: C Interface Code
370
1
12.3.3 Xcption: Low-Level Module
371
15
12.4 MIPS Interrupts
386
2
12.5 Tuning for MIPS
388
7
Appendix A Instruction Timing and Optimization
395
8
A.1 Avoiding Hazards: Making Code Correct
395
1
A.2 Avoiding Interlocks to Increase Performance
396
1
A.3 Multiply Unit Hazards: Early Modification of hi and lo
397
1
A.4 Avoiding Coprocessor O Hazards: How Many nops?
398
2
A.5 Coprocessor O Instruction/Instruction Scheduling
400
1
A.6 Coprocessor O Flags and Instructions
401
2
Appendix B Assembler Language Syntax
403
6
Appendix C Object Code
409
14
C.1 Tools
411
1
C.2 Sections and Segments
411
2
C.3 ECOFF (RISC/OS)
413
4
C.3.1 File Header
413
1
C.3.2 Optional a.out Header
414
2
C.3.3 Example Loader
416
1
C.3.4 Further Reading
416
1
C.4 ELF (MIPS ABI)
417
4
C.4.1 File Header
417
1
C.4.2 Program Header
418
1
C.4.3 Example Loader
419
2
C.4.4 Further Reading
421
1
C.5 Object Code Tools
421
2
Appendix D Evolving MIPS
423
8
D.1 MIPS16
423
3
D.1.1 Special Encodings and Instructions in MIPS16
424
1
D.1.2 MIPS16 Evaluated
425
1
D.2 MIPS V/MDMX
426
5
D.2.1 Can Compilers Use Multimedia Instructions?
427
1
D.2.2 Applications for MDMX
428
1
D.2.3 Applications for MIPS V
428
1
D.2.4 Likely Success of MDMX/MIPS V
429
2
MIPS Glossary
431
38
References
469
2
Books and Papers
469
1
On-Line Resources
470
1
Index
471