search for books and compare prices
Tables of Contents for Vlsi Design
Chapter/Section Title
Page #
Page Count
Preface
v
Introduction
1
28
VLSI Design Methodology
3
1
VLSI Design --- An Overview
4
19
Summary
23
1
To Probe Further
24
3
Problems
27
2
CMOS Logic Circuits
29
40
nMOS Switch Model
29
3
pMOS Switch Model
32
2
CMOS Inverter
34
4
CMOS Logic Structures
38
1
Complementary Logic
39
12
Pass-Transistor/Transmission-Gate Logic
51
9
Summary
60
1
To Probe Further
61
1
Problems
62
7
IC Layout and Fabrication
69
32
CMOS IC Fabrication
69
9
CMOS Design Rules
78
6
Layout Examples
84
13
Summary
97
1
To Probe Further
97
1
Problems
98
3
CMOS Circuit Characterization
101
46
MOSFET Theory
101
4
Voltage Transfer Characteristic
105
4
Circuit-Level Simulation
109
3
Improved MOSFET Switch Model
112
4
Resistance/Capacitance Estimation
116
7
RC Timing Model
123
3
Transistor Sizing
126
4
τ-Model
130
5
Driving Large Loads
135
3
Power Dissipation
138
2
Latch-Up
140
2
Summary
142
1
To Probe Further
142
1
Problems
143
4
Sequential Logic Circuits
147
28
General Structure
147
3
Asynchronous Sequential Logic Circuits
150
3
D-Latch
153
4
D-Flip-Flop
157
2
One-Phase Clock Systems
159
1
Two-Phase, Non-Overlapping Clock Systems
160
4
Clock Distribution
164
1
Sequential Circuit Design
165
4
Summary
169
1
To Probe Further
170
1
Problems
170
5
Alternative Logic Structures
175
24
Complementary Logic Circuits
175
1
Pass-Transistor/Transmission-Gate Logic
176
1
Pseudo-nMOS Logic
177
5
Programmable Logic Array
182
3
Dynamic CMOS Logic
185
5
Domino Logic
190
2
Dynamic Memory Elements
192
1
BiCMOS Logic Circuits
193
1
Summary
194
1
To Probe Further
195
1
Problems
196
3
Sub-System Design
199
30
Adders
200
9
Full Adder Tree
209
2
Parallel Multipliers
211
8
Read-Only Memory
219
2
Random Access Memory
221
4
Summary
225
1
To Probe Further
225
1
Problems
226
3
Chip Design
229
24
Microprocessor Design Project
230
14
Field Programmable Gate Array
244
6
Summary
250
1
To Probe Further
251
1
Problems
251
2
Testing
253
28
Fault Models
255
3
Test Generation (Stuck-at Faults)
258
3
Path Sensitization
261
1
D-Algorithm
262
4
Test Generation for Other Fault Models
266
1
Test Generation Example
267
3
Sequential Circuit Testing
270
1
Design-for-Testability
271
1
Built-In Self-Test
272
5
Summary
277
1
To Probe Further
277
1
Problems
278
3
Physical Design Automation
281
30
Layout Generators and Editors
281
2
Placement and Routing
283
1
Floorplanning and Placement
283
7
Routing
290
15
Summary
305
1
To Probe Further
306
2
Problems
308
3
Parallel Structures
311
30
Parallel Architectures
311
3
Interconnection Networks
314
8
Pipelining
322
4
Pipeline Scheduling
326
3
Parallel Algorithms
329
7
Summary
336
1
To Probe Further
337
1
Problems
337
4
Array Processors
341
36
Array Processing Examples
342
6
Array Processor Design
348
17
Wavefront Array Processor
365
9
To Probe Further
374
1
Problems
375
2
Fault Tolerant VLSI Architectures
377
20
Reliability
377
4
Fault Tolerant Design
381
1
Fault Tolerant VLSI Arrays
382
1
Set Replacement Algorithm
383
4
Shifting Replacement Algorithm
387
2
Fault Stealing Replacement Algorithm
389
3
Compensation Path Replacement Algorithm
392
1
Summary
393
1
To Probe Further
394
1
Problems
395
2
Index
397