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Tables of Contents for Hardware Design and Petri Nets
Chapter/Section Title
Page #
Page Count
Preface
vii
Part I Hardware Modelling using Petri Nets
Comprehensive Causal Specification of Asynchronous Controller and Arbiter Behaviour
3
30
Ralf Wollowski
Jochen Beister
Complementing Role Models with Petri Nets in Studying Asynchronous Data Communications
33
18
Fei Xia
Ian Clark
Petri Net Representations of Computational and Communication Operators
51
26
David H. Schaefer
James H. Sosa
Part II Model Analysis and Verification for Asynchronous Design
Properties of Change Diagrams
77
16
Uwe Schwiegelshohn
Lothar Thiele
LTrL-based Model Checking for a Restricted Class of Signal Transition Graphs
93
14
R. Meyer
P.S. Thiagarajan
A Polynomial Algorithm to Compute the Concurrency Relation of a Regular STG
107
22
Andrei Kovalyov
Part III Theory and Practice of Petri Net Based Synthesis
Synthesis of Synchronous Digital Systems Specified by Petri Nets
129
22
Norian Marranghello
Jaroslaw Mirkowski
Krzysztof Bilinski
Deriving Signal Transition Graphs from Behavioral Verilog HDL
151
20
Ivan Blunno
Luciano Lavagno
The Design of the Control Circuits for an Asynchronous Instruction Prefetch Unit Using Signal Transition Graphs
171
22
Suck-Heui Chung
Steve Furber
Part IV Hardware Design Methods and Tools
Electronic System Design Automation Using High Level Petri Nets
193
12
Patrik Rokyta
Wolfgang Fengler
Thorsten Hummel
An Evolutionary Approach to the Use of Petri Net based Models
205
18
Ricardo J. Machado
Joao M. Fernandes
Antonio J. Esteves
Henrique D. Santos
Modelling and Implementation of Petri Nets Using VHDL
223
16
Dave Prothero
Part V Architecture Modelling and Performance Analysis
Performance Analysis of Asynchronous Circuits and Systems using Stochastic Timed Petri Nets
239
30
Aiguo Xie
Peter A. Beerel
Performance Analysis of Dataflow Architectures Using Timed Coloured Petri Nets
269
22
B.R.T.M. Witlox
P. van der Wolf
E.H.L. Aarts
W.M.P. van der Aalst
Modeling a Memory Subsystem with Petri Nets: a Case Study
291
20
Matthias Gries
Performance Modeling of Multithreaded Distributed Memory Architectures
311
Wlodek M. Zuberek