Tables of Contents for System Design
Chapter/Section Title
Page #
Page Count
Table of Contents
v
 
Preface
ix
 
Acknowledgement
xiii
 
The SpecC Language
1
62
Outline
2
1
Introduction
3
2
Computational Models
5
7
Finite State Machine
6
1
Data Flow Graph
7
1
Finite State Machine with Datapath
8
1
Super-State Finite State Machine with Datapath
9
1
Hierarchical Concurrent Finite State Machine
10
1
Program State Machine
11
1
The SpecC Model
12
14
Traditional Model
12
2
SpecC Model
14
1
Protocol Inlining
15
2
Plug-and-Play with Computation
17
5
Plug-and-Play with Communication
22
4
System-level Language Requirements
26
3
Language Goals
26
2
Language Requirements
28
1
The SpecC Language
29
31
Foundation
29
4
Types
33
2
Structural Hierarchy
35
3
Behavioral Hierarchy
38
2
Finite State Machine Execution
40
1
Pipeline Execution
41
4
Communication
45
3
Synchronization
48
3
Exception Handling
51
2
Timing
53
4
Library Support
57
1
Persistent Annotation
58
2
Summary and Conclusion
60
3
Summary
60
1
Conclusion
61
1
Further Information
62
1
Modeling and Design with SpecC
63
112
Outline
64
1
Introduction
65
7
Abstraction Levels
66
3
Design Flow
69
2
SpecC Methodology
71
1
Specification Model
72
8
Specification Model Example
73
3
Communication versus Computation
76
4
Architecture Refinement
80
24
Behavior Partitioning
82
9
Variable Partitioning
91
6
Execution Time
97
2
Scheduling
99
5
Architecture Model
104
2
Communication Synthesis
106
45
Channel Partitioning
108
8
Protocol Insertion
116
22
IP Components
138
4
Protocol Inlining
142
9
Communication Model
151
1
Backend
152
19
Hardware Synthesis
154
3
Software Synthesis
157
3
Interface Synthesis
160
7
Implementation Model Example
167
4
Implementation Model
171
1
Summary and Conclusions
172
3
Design of a GSM Vocoder
175
18
Outline
176
1
Introduction
177
2
GSM Vocoder Standard
178
1
Specification Model
179
3
Encoding Hierarchy
180
1
Profiling
181
1
Architecture Exploration
182
3
Estimation
183
2
Architecture Model
185
1
Communication Synthesis
186
1
Communication Model
187
1
Backend
188
2
Implementation Model
190
1
Summary & Conclusions
191
2
Design of a JBIG Encoder
193
24
Outline
194
1
Introduction
195
2
JBIG Block Diagram
196
1
Specification
197
2
Specification Model
198
1
Partitioning
199
8
Solution 1
200
1
Solution 2
201
1
Solution 3
202
1
Solution 4
203
1
Results
204
2
Selection
206
1
Architecture Model
207
1
Communication model
208
5
Memory-Bus Interface
209
4
JBIG Hardware Design
213
2
JBIG Hardware Architecture
214
1
Conclusions
215
2
SpecC Design Environment
217
20
Outline
218
1
Introduction
219
5
System Validation
221
1
SpecC Scope
222
1
SpecC Methodology
223
1
Refinement
224
6
User Interface
225
1
Profiling and Estimation
226
1
Interactive Refinement
227
1
Automatic Refinement
228
1
Validation
229
1
SpecC Engine
230
4
Refinement Engine
231
1
Exploration Engine
232
1
Synthesis Engine
233
1
Conclusions
234
3
References
235
2
SpecC Technology Open Consortium
237
16
Introduction
238
1
Motivation
238
8
Productivity Gap
239
1
SpecC Technology
240
6
The SpecC Technology Open Consortium
246
7
Purpose
247
1
History
248
1
Plans
249
1
Membership
250
3
Index
253