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Tables of Contents for Synchronous Equivalence
Chapter/Section Title
Page #
Page Count
List of Figures
ix
 
List of Tables
xi
 
Introduction
1
10
Emergence of Embedded Systems
1
2
Design of Embedded Systems
3
2
Requirements For An Effective Design Methodology
5
1
Proposed Design Approach
6
2
Motivation
8
1
Overview
9
2
The Polis Codesign Framework
11
12
The Polis Codesign Methodology
12
11
High Level Language Translation
14
4
Implementing CFSM Networks
18
2
System Co-Simulation
20
1
Synthesis
21
2
Codesign Finite State Machines
23
18
Background
23
4
Hierarchical Process Network
23
2
Finite State Machines
25
1
Extended Finite State Machines
26
1
CFSMs: Semantics
27
3
Signals
28
1
Process Behavior
28
1
Network Behavior
29
1
Mathematical Model
30
11
Preliminaries
30
1
Finite Automata
30
2
Signals
32
1
Transitions
33
1
CFSM
33
1
Semantics of CFSM
33
1
Input buffer automata
34
2
Output buffer automata
36
1
Main automaton
37
2
Networks of CFSMs
39
2
Formal Verification of CFSM Specifications
41
16
Verification Methodology
44
1
Verification Example: Seat Belt Alarm Controller
45
4
Verification Example: Shock Absorber Controller
49
6
Verifying Property P1.1
53
1
Verification with Abstracted Integers
53
1
Verification Under Timing Assumptions
54
1
Verifying Property P1.2
54
1
Timing Assumptions and Freeing Variables
55
1
Verifying Property P1.3
55
1
Conclusions
55
2
Synchronous Equivalence
57
10
Motivation
59
1
The Synchronous Assumption and Synchronous Equivalence
60
2
Related Work
62
1
Design Exploration Methodology
62
1
Analyzing Synchronous Equivalence
63
4
Static Equivalence Analysis
67
14
Scheduling Policy Analysis
67
7
Validating Experiment: Seat Belt Alarm Controller
72
2
System Graph Analysis
74
3
Mixed Analysis
77
1
Analysis of Heterogeneous Architectures
78
1
Conclusions
78
3
Communication Analysis
81
26
Execution Trace
81
4
Abstracting Communication
85
21
Containers
85
3
Well-Behaved Scheduling Policy
88
1
Execution Covers
89
3
Greatest Execution Covers
92
1
Simple Illustrating Example
92
1
Shock Absorber Example
93
4
Seat Belt Alarm Controller Example
97
1
Least Execution Covers
97
3
Simple Illustrating Example
100
1
Seat Belt Alarm Controller Example
100
3
ATM Switch Example
103
1
Correctness Proof
104
2
Conclusions
106
1
Refining Communication Analysis
107
20
Container Refinement
108
9
State Refinement
117
4
Pruning Execution Covers
121
3
Relationship with Exact Simulation
124
3
Conclusions and Future Directions
127
1
Conclusions
127
1
Future Directions
128
1
Iterative Refinement Techniques
128
1
Component Repartitioning
129
1
Multi-Clock Synchronous Systems
129